This invention relates to verification of fuse/pass transistor combinations in routing structures, and more particularly to the verification of these combinations in multi-level routing structures.
Programmable interconnect devices permit a user to programmably route signals between pins of the device. For example, Lattice Semiconductor currently manufactures an ispGDX(copyright) and ispGDXV(copyright) family of programmable interconnect devices having a non-volatile E2CMOS(copyright) in-system-programmable crossbar switch matrix for programmable switching, interconnect, and jumper functions. In an ispGDXV(copyright) device, each pin is associated with an input/output (I/O) circuit that programmably couples other I/O circuits through a routing structure that may be denoted as a global routing pool (GRP). Another programmable interconnect circuit is described in xe2x80x9cBlock Oriented Architecture for a Programmable Interconnect Circuit,xe2x80x9d U.S. Ser. No. 10/022,464, filed Dec. 14, 2001, the contents of which are hereby incorporated by reference in their entirety. In this programmable interconnect circuit, the I/O circuits are grouped into block to form a xe2x80x9cblock-orientedxe2x80x9d architecture that contrasts with conventional xe2x80x9cpin-orientedxe2x80x9d architectures for a programmable interconnect circuit. In a pin-oriented architecture, the routing structure addresses each I/O circuit independently, whereas in a block-oriented architecture, the I/O circuits within a block are not addressed independently by the routing structure. By organizing the I/O circuits into blocks, the routing structure may be arranged in a two-level organization as described in xe2x80x9cMulti-Level Routing Structure for a Programmable Interconnect Circuit,xe2x80x9d U.S. Ser. No. 10/023,053, filed Dec. 14th, 2001, the contents of which are hereby incorporated by reference in their entirety. In addition, the routing structure may be subdivided into a data-path routing structure and a control-path routing structure as described therein.
Regardless of whether a routing structure is one level or two-level, each routing structure functions by connecting a given input conductor to a given output conductor through a pass transistor or pass gate. Each pass gate is controlled by a memory cell (the fuse) and is either conducting or non-conducting depending upon the bit stored in the memory cell. For example, should the memory cell be storing a xe2x80x9c1,xe2x80x9d its corresponding pass gate may be conducting. Conversely, should the memory cell be storing a xe2x80x9c0,xe2x80x9d the corresponding pass gate may be nonconducting. Thus the state of the memory cell controls whether the corresponding input and output conductors are coupled. To function properly, each pass gate in a routing structure must be able to pass or block both a xe2x80x9c0xe2x80x9d and a xe2x80x9c1.xe2x80x9d Before shipping a routing-structure-equipped device, a manufacturer will typically test the routing structure using a xe2x80x9cverifyxe2x80x9d scheme. For example, the input conductor coupled to the pass transistor carries a test signal and the output signal carried by the output conductor coupled to the pass transistor is tested for both states of the corresponding memory cell. During verification, the output signal may be pulled to the inverted state of the test signal through a xe2x80x9cweakxe2x80x9d inverter. Because the output signal is only weakly pulled to the inverted state of the test signal, the output signal should equal the test signal when the pass gate is activated. If the pass gate is nonconducting, the output signal should equal the inverted test signal as pulled by the weak buffer.
For example, assume that a pass transistor is configured such that it conducts when its memory cell stores a xe2x80x9c1xe2x80x9d and is non-conducting when its memory cell stores a xe2x80x9c0.xe2x80x9d During verification, the test signal may be set to xe2x80x9c0xe2x80x9d and the output signal from the pass transistor tested for both states of the memory cell. When the memory cell stores a xe2x80x9c1,xe2x80x9d the output signal should be a xe2x80x9c0xe2x80x9d such that the pass gate can xe2x80x9cpass a 0.xe2x80x9d Conversely, when the memory cell stores a xe2x80x9c0,xe2x80x9d the output signal should be a xe2x80x9c1xe2x80x9d such that the pass gate can xe2x80x9cblock a 0.xe2x80x9d Similarly, when the test signal is xe2x80x9c1,xe2x80x9d the pass gate should be able to both xe2x80x9cblock a 1xe2x80x9d and xe2x80x9cpass a 1,xe2x80x9d depending upon the state of the memory cell. Although a user of a routing-structure-equipped device is assured that the manufacturer has already verified its operation, each user must be assured that the programming equipment used to program the routing structure and its associated cabling are working correctly. Thus, the user will program the fuses with a test pattern, supply a known set of input signals, and verify that the desired set of output signals as determined by the programming is received. Thus, both the manufacturer and user will typically verify operation of the routing structure.
Two-level routing structures such as disclosed in U.S. Ser. No. 10/023,053 require new approaches to verify schemes, particularly with respect to testing the second level routing structure efficiently. Accordingly, there is a need in the art for improved verify schemes for routing structures, particularly two-level routing structures.
In accordance with a first aspect of the invention, a multi-level routing structure is provided having a user mode and a verify mode using a test signal. The multi-level routing structure includes a first-level routing structure that, in the user mode, receives a first set of input signals and routes this set of signals through a first switch matrix to form a first set of output signals. In the verify mode, the first-level routing structure routes the test signal, rather than the first set of input signals, through the first switch matrix to form the first set of output signals. A second-level routing structure, during the user mode, receives the first set of output signals and routes these signals through a switch matrix into a second set of output signals. In the verify mode, the second-level routing structure routes the test signal, rather than the first set of output signals, through the second switch matrix to form the second set of output signals. A sense gate is operable in the verify mode to receive the first set of output signals or the second set of output signals, the sense gate being configured to weakly invert the test signal and combine the inverted test signal with the received set of output signals to form a set of verification signals.
In accordance with another aspect of the invention, a multi-level routing structure is provided having a user mode and a verify mode using a test signal. The multi-level routing structure includes a first-level routing structure that receives a first set of input signals and routes the received signals through a first switch matrix to form a first set of output signals during the user mode. In the verify mode, the first-level routing structure routes the test signal, rather than the first set of input signals, through the first switch matrix to form the first set of output signals. A second-level routing structure, during the user mode, receives the first set of output signals and routes these signals through a switch matrix into a second set of output signals. In the verify mode, the second-level routing structure routes the test signal through the second switch matrix to form a third set of output signals, wherein the size of the third set of output signals equals the size of the first set of output signals. A sense gate is operable in the verify mode to receive the first set of output signals or the third set of output signals, the sense gate being configured to weakly invert the test signal and combine the inverted test signal with the received set of output signals to form a set of verification signals.
The invention will be more fully understood upon consideration of the following detailed description, taken together with the accompanying drawings.